Routing Help Guide
Allegro - output SPECCTRA Design file using SPIF Interface.
OrCAD - output .cct file.
PowerPCB - native binary PCB file; no output required.
PADS-Perform - output ASCII-OUT, ALL, current units.
PADS-2000 - output ASCII-OUT, ALL, current units.
PCAD200x - Save ASCII version of PCB
AccelEDA - save ASCII version of PCB.
P-CAD - output PDIF with embedded apertures. Also requires Layer Map file.
TangoDOS - ASCII
Mentor - complete PCB directory and ASCII_GEOMS
Protel - ASCII
CBDS - outputs SPECCTRA Design file
Separate grids for wires and vias can be specified. The grids should NOT be designed to control DRC values but rather to WORK WITH specified DRC values.
Protect Existing Routing
Any pre-routed wiring can be protected and therefore not disturbed by the router.
Signal nets - specifies the default widths for signal nets. Signal nets are any nets not defined as a power plane. These include wider 'power' traces that are routed as wires rather than planes.
Power nets - nets as connecting to power planes. Specify the maximum width for fanouts from caps to a power plane. Power nets will taper down to the width of smd pads for fine-pitch parts. 'Power' routed nets (not on a plane) carrying larger currents are specified elsewhere as individual net widths under 'Net Widths'.
Clearances are measured from edge to edge. The router does not see copper fills (pours) which should be replaced with wire-keepouts. Clearances are applied to these objects:
Wires - routing traces.
Vias - must be defined in the host CAD system as a legal via.
SMD - surface mount pads.
PIN - thru-hole pin.
Area - area is an all-encompassing category that includes solid copper areas and keepouts.
Board edge - true board outline.
These vias are used for routing signal wires. Separate via types can be defined for routing to power planes but it is not necessary to define separate power vias. Blind vias can be inserted in SMD pads. We can accommodate all requirements for laser and plasma microvias. Options for blind vias in SMD pads include locate at PAD origin only and contain completely with SMD pad.
Power Vias to Power Plane
Separate power vias can be defined for connection of power nets to power planes. Power planes includes ground and voltage planes - it is generic term in the router. The power via is defined by net.
Power Via Routing Styles
This impacts how decoupling caps are managed. Direct connections allow power pins on SMDs and caps to independently connect to a power plane. Sharing a common via to the plane between an SMD pad and a decoupling cap typically occurs when the cap and pad are on opposite sides of the board. SMD pad to decoupling cap to via to power plane forces the decoupler to filter the signal prior to connection to the via.
Keepouts and Fiducials
Keepouts can be applied to all layers or selectively to individual layers. You should specify a wire keepout as a substitute for a copper fill (pour). If your host CAD system cannot easily create keepouts, we can dynamically create them in the router.
Fiducials will NOT translate to the router unless they are legally defined as an smd pad (including a terminal point). If you do not create fiducials as a part, then you must substitue a keepout for the fiducial or the router will not see the fiducial and will route thru the fiducial location.
Fences define boundaries for the router. A full fence allows routing ONLY within the fence. Soft fences are used for mixed-technology (analog-digital boards). A soft fence keeps digital signals out of the analog area and all I/O between the analog and digital areas to cross the soft fence boundary.
Each layer of the board must be defined as either a signal layer or a power plane. The router does not support mixed layers (part signal and part plane). If you require a mixed plane layer, we can help you organize effective workaround strategies. The router recognizes split power planes. Some CAD systems translate split boundaries to SPECCTRA, some do not. In all cases, the router will understand multiple power nets on a split plane. Please list the power and geround net names found on each power layer.
A signal layer that is not to be routed on is termed OFF. An outer layer which is off will still fanout smd pins to a fanout via in order to route internally.
Please list the layer name as defined in your host CAD system for each layer in your database. It is imperative that you list the layers in the order that the board will be built (stackup) if adjacent layer crosstalk will be managed.
Daisy-chain Nets to be Ordered
Daisy-chain nets (ECL routing) can be specified in several ways.
Daisy-chain only - routes sequentially. Router does not schedule to minimize length.
Source and/or Termination - routes daisy-chain between source and/or termination. Router does not schedule to minimize length.
Ordered Daisy-chain - routes daisy-chain based on the explicit order of the class or net. Allows best path to be specified.
Controls maximum stub length to minimize reflections on daisy-chain nets. We recommend some stub length rather than a zero stub length. A zero stub length forces two vias in order to route in and out of every smd pad.
You may specify complex topology routing for classes and nets by net segments. The router can insert a virtual pin for splitting a routing path between pins.
Right Way Routing
The router naturally follows alternating horizontal and vertical layer directions. This bias towards horizontal and vertical routing can be dramatically increased or decreased. Strong right way routing (following more the direction of the layer) looks more 'hand-routed' and is easier for manual editing for ECOs. Strong right way routing increases the via count and is not a reliable method for controlling adjacent layer crosstalk, as the router will still go 'wrong way' near the board edges. To control adjacent layer crosstalk, use the true crosstalk controls (adjacent layer paralelism control or adjacent layer noise-coupling control).
Nets by Layer
Classes, nets and net segments can be routed on specified layers. If nets are routed on an smd design on internal layers only, the router will automatically fanout to get off the outer smd layer onto the correct inner layer(s). You may specify ONLY certain nets and no others to route on particular layers.
Nets by Clearance
Minimum clearances can be set for classes, net and net segments. These clearances are measured from the edge of the wire to specific objects. For minimum crosstalk control, the clearance should be specified as wire-to-wire. For minimum arc gap control, the clearance should be specified from the wire to all objects. For fine-pitch smd parts, wires can be routed on internal layers with larger clearances only on the routing layers, allowing a small length to a fanout via on outer layers unaffected by the clearance rule.
Specific clearances between selected classes can be specified. This allows isolation between classes that should not couple and is a preferred alternative to forcing these classes onto different layers. For busses, a class-to-itself clearance can be defined, allowing a data or address bus that switches simultaneously to route closer to itself than to other nets.
Nets by Width
Widths for classes, nets and net segments can be specified. You may also specify different widths by layer for class, net and net segment. This allows specifying controlled impedance designs.
For nets that are not daisy-chained, you can specify the style of routing you prefer. Allowing t-junctions lets one wire abut a second wire at a 'T'. This saves vias and produces cleaner connections on the outer layers of smd designs. Selecting NO t-junctions allows t-junctions to occur only at a via or pin.
Specify what type of nets will require a testpoint. The router will create one testable via for each of the specified nets. It does not produce testpoints for power plane nets. Signal nets are named nets in the netlist with more than one pin. Single pin nets are electrically active named nets with only one pin. Unconnected pins are not defined in the netlist and are electrically unconnected.
Testpoints are probed based on a minimum center-to-center spacing. This is not related to the routing grid, although we will add testable vias on the same grid as the via grid unless otherwise requested.
Clearance to Part Edge
The testpoint probe must physically clear any parts mounted on the side of the board being probed. This clearance DRC accomodates the diameter of the test probe tip.
Test Point Side
The board can be probed from top, bottom or both sides (clamshell or flying head).
Use Component Pins
Allows thru-hole pins to be probed as well as testable vias.
Testpoints are accorded full DRC clearances to other objects.
TestPoint Vias to Use
Particular via types can be defined as testable vias (testpoints). If you elect to use thru-hole vias for testing that require a larger probable pad diameter than the routing via, it is not necessary to define this large pad diameter on all layers. Rather, define this testable via with the same diameter pad as the routable via except make the pad on the probe layer alone larger. This allows the testable via to easily replace existing vias. Surface mount testable vias can also be defined and used for testpoints. A combination of thru-hole and SMD testable vias produces the most complete results.
Enhanced Routing Options
The total number of vias can be aggressively reduced from 25-40% less than the router otherwise produces. This requires special pre-processing and adds to the router's overhead. Specific nets or classes of nets can additionally be specified for maximum allowable vias.
Shields can be automatically generated for selected nets. The shield net must be a voltage or ground used on a power plane. The shield can be specified as open-ended or closed. A single via is used for attaching each shield segment to its plane. The width of the shield, the gap between the shield and shielded net, and the minimum length of a shielded segment can be specified.
Minimum and maximum lengths can be specified for nets or segments of nets. Lengths can be quantitatively specified as actual values, or lengths can be qualitatively specified as a percentage of rat's nets manhattan length. By specifying as a percentage, you can control the relative lengths of classes as a sensitivity tool. For instance, clocks could be shorter than data, data shorter than address. We recommend controlling the length of all nets as a percentage of manhattan length in order to filter out long, circuitous routes. Lengths can also be specified as time delay units based on speed of propagation per layer. Time equivalencies can be computed by DFM using AutoTools.
Complete nets or segments of nets can be matched within a specified tolerance. Matched lengths are best accomplished with an accordian pattern with a fixed distance between accordian sections while allowing a flexible height.
Two nets specified as differential will be routed as an adjacent pair following a similar path. A gap can be specified between the differential wires which overrides other clearance specs.
CrossTalk X-Y Parallelism
The router manages same layer parallelism geometrically by limiting and separating adjacent traces. The router will progressively separate adjacent traces based on length of parallelism in order to diminish potential same layer crosstalk.
CrossTalk Z-Axis Parallelism
The router manages adjacent layer parallelism geometrically by limiting and separating overlapping traces. The router will progressively separate overlapping traces based on length of overlap in order to diminish potential adjacent layer crosstalk.
CrossTalk X-Y Noise Coupling
The router manages the maximum acceptable noise on target classes of nets by accumulating coupled noise from adjacent wires on the same layer. Uses AutoTools and the Quantic Engine to simulate accurate field coupling values from sources of noise. DOES NOT REQUIRE ELECTRICAL MODELS.
CrossTalk Z-Axis Noise Coupling
The router manages the maximum acceptable noise on target classes of nets by accumulating coupled noise from adjacent layers. Uses AutoTools and the Quantic Engine to simulate accurate field coupling values from sources of noise. DOES NOT REQUIRE ELECTRICAL MODELS.